Method of fabricating a read only memory in MOS technology, and memory thus obtained
US5679594A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1996 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Jan 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A method of fabricating a read only memory consisting of a matrix of arrays of enhancement-mode or depletion-mode programmed MOS transistors that consists, on a silicon substrate (SU) of a first conduction type, in defining by masking, retrograde wells of the same conduction type as that of the substrate, and then retrograde wells of conduction type opposite to that of the substrate. Removal of the protective oxide allows thus to predefine the enhancement-mode and depletion-mode transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.