Customizable three metal layer gate array devices
US5679967A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1995 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Mar 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three metal layer customizable gate array devices and techniques to customize them are disclosed. Such a device incorporates an integrated circuit blank having a plurality of transistors and at least three metal layers. A plurality of fusible links interconnects said plurality of transistors into an inoperable circuit. A laser ablative etch resistant coating is formed over the device. Later, the coating is ablated by laser at locations overlaying designated fuse locations. The device is then etched for selectably removing some of the fusible links, thereby converting the inoperable integrated circuit blank into an operable gate array device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.