Triple gate flash-type EEPROM memory and its production process
US5679970A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1995 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Feb 2, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory including a semiconductor substrate, an array of memory cells mutually electrically insulated by side insulators, wherein each memory cell includes a gate stack consisting of a gate insulator, a floating gate and a control gate separated by an electrical insulator between the gates, said gate insulator being arranged between the floating gate and the substrate, a source and a drain formed in the substrate on either side of said stack and outside the side insulators, an erasing gate located above the source in partial overlap with the stack, and electrically insulated from the source and said stack by a thin insulator, as well as conductive strips for applying electrical signals to the gate stacks, erasing gates, sources and drains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.