Level converter for CMOS 3V to from 5V
US5680064A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 28, 1996 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | May 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source, and converts an output signal of the first circuit system into an input signal of the second circuit system. The second cir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.