Memory architecture for reformatting and storing display data in standard TV and HDTV systems
US5680156A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1994 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Nov 2, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/1934
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane (60). The memory plane (60) comprises an input bus, an m.times.n array of memory cells (80) in communication with the input bus, and an m-bit-wide output bus. The array of memory cells (80) receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.