High-speed, non-volatile electrically programmable and erasable cell and method
US5680346A · kind A · utility
33Cited by
15References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile programmable circuit having programming and read bitlines, a non-volatile memory cell, and a read select transistor, and a method for its operation. The non-volatile memory cell is programmable through the programming bitline. The read select transistor is connected between the non-volatile memory cell and the read bitline. During read operation, the programming bitline is grounded and programmed information is readable onto the read bitline. During programming operation, the read bitline is grounded, and programmed information is programmable into the non-volatile memory cell for storage and retention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.