Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US5680422A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/073
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.