Lookaside buffer for inputting multiple address translations in a computer system
US5680566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1995 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Mar 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address, then these entries are invalidated. If the translation table must be searched then the method involves retrieving from the translation table, and inserting into the TLB, a translation for the specified input address and possibly one or more translations for other input addresses stored with the translation for the specified input address in one node of the B-tree implementing the translation table. When a particular input address retrieved from the translation table is in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.