Method and system for processing multiple requests for data residing at the same memory address
US5680577A · kind A · utility
11Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.