System for interconnecting stacked integrated circuits
US5682062A · kind A · utility
279Cited by
40References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. the via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies 335a, 335b, 335c with conductive vias are stacked on top of each other. Other dies 341, 343 are connected together with an optical coupling die 342.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.