Low capacitance bus driver
US5682110A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 1992 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Mar 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low capacitance bus driver circuit includes, in this example, P-channel and N-channel output transistors with input gates connected by means of CMOS pass gates to a common input terminal and having respective P-channel and N-channel transistors connected to the input gates of the output transistors so as to place them in a high impedance state when the CMOS pass gates are disabled. Input capacitance of the bus driver circuit is greatly reduced by elimination of CMOS gate capacitance when the bus driver is enabled. When the bus driver is not enabled, it provides optimal performance of a single gate delay from input to output without the need for series connected output devices or correspondingly higher input capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.