Method and apparatus for reducing phase lag resulting from digital to analog conversion
US5682159A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1996 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Feb 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for implementing a zero order hold function in the digital to analog conversion process in a digital control system reduces the phase lag contributed by the digital to analog conversion process relative to a conventional implementation of the zero order hold function. The apparatus for implementing the reduced phase lag zero order hold function employs a digital signal processor, a plurality of digital buffers, a digital multiplexing element, and a digital to analog converter. Phase lag is reduced by generating, from the digital to analog converter, for a fraction of the sample period, a waveform having a constant analog voltage with an amplitude which is scaled by the reciprocal of said fraction relative to a conventional zero order hold function. During the remainder of the sample period a substantially constant offset analog voltage is generated by the digital to analog converter. Alternatively, the time compression and amplitude scaling required to implement the reduced phase lag zero order hold function can be performed within the digital signal processor in the digital control system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.