High-order delta sigma analog-to-digital converter with unit-delay integrators
US5682160A · kind A · utility
Inventors
Key dates
| Filing date | May 20, 1996 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | May 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delta sigma modulator which enables each cascaded integrator to settle independently within a full clock period and uses binomial coefficients in the feedback paths to obtain the required sinusoidal shaping of quantizer error, achieves an increase in both the sampling rate and the order to improve resolution. Using a multi-bit quantizer also improves modulator resolution. In one embodiment, the modulator includes a plurality of cascaded unit-delay integrators and utilizes binomial coefficient scaling in the feedback loop. A multi-bit analog-to-digital converter is coupled to receive the output signal of the cascaded unit-delay integrators. The feedback loop includes a multi-bit digital-to-analog converter coupled to the output of the multi-bit analog-to-digital converter. The output of the digital-to-analog converter is coupled to the inputs of at least the first and second differential summing junctions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.