High-order delta sigma modulator
US5682161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1996 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | May 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delta-sigma modulator includes, in one embodiment, cascaded unit-delay integrators, the number of which is selected depending upon the order desired. The modulator further includes an n-bit (or multi-bit) A/D converter coupled to the output of the last cascaded integrator, and an n-bit (or multi-bit) D/A converter coupled to the output of the A/D converter. A truncator also is coupled to the output of the A/D converter. Truncation error correction is performed digitally by a truncation corrector. A one-bit D/A converter provides feedback from the output of the truncator to differential summing junctions interposed at the input of each unit-delay integrator. The multi-bit D/A converter output signal is fed back to differential summing junctions at the input of the third order and higher unit-delay integrators. The multi-bit D/A converter requires no digital correction of its linearity and only unit-delay integrators are used so that N-1 delay free integrators do not all have to settle within one clock period. The modulator therefore utilizes multiple quantizer bits to provide increased converter resolution and is stable at high orders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.