Deadlock avoidance for switched interconnect bus systems
US5682485A · kind A · utility
7Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1996 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Aug 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deadlock avoidance system for avoiding interconnection deadlocks between a plurality of data transfer devices includes a controller, a switch interconnector coupled to all of said data transfer devices for interconnecting on a one-to-one basis selected ones of the data transfer device as requesting units to selected ones of said data transfer devices as receiving units. A transfer queue is employed that includes a master transfer register and a slave transfer register, a master register, a slave register and a target register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.