Low power set associative cache memory with status inhibit of cache data output
US5682515A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1996 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Jun 10, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus. Additionally, the data output of the cache data RAM (30) is inhibited unless it is determined that the cache data stored in the cache data RAM (30) is valid, this information stored in a status RAM (62).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.