Method for reducing power consumption of switching nodes in a circuit
US5682519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1995 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Apr 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a low-power circuit from a Shannon graph having a plurality of primary inputs, a plurality of nodes including parent and child nodes, a first end-terminal, and a second end-terminal, each of the plurality of nodes having output edges associated therewith, includes the steps of: substituting the plurality of nodes and associated output edges with a plurality of cells, one cell for each node and output edge associated therewith, each cell including a plurality of elements; coupling a cell substituted for a parent node to cells substituted for child nodes of the parent node; and bypassing particular elements of child nodes having only one parent node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.