Array processor for morphological image processing
US5682520A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1996 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Feb 15, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S345/955
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The array processor includes a grid of individual morphological processing elements formed on a VLSI chip. Each element of the grid includes a photo-detector for directly sensing a pixel of an image projected upon the chip. A signal generated by the photo-detector is sensed by a threshold circuit which outputs a binary value having a value depending upon the intensity of the light detector by the photo-detector. Each element also includes morphological processing circuitry for manipulating the binary value received from the threshold detector in accordance with predetermined morphological processing operations and in accordance with binary values received from adjacent processing elements. After modification of the binary value by application of one or more morphological processing operations, the binary value of each processing element is used to control a respective LCD element for displaying a pixel of a modified image. In this manner, all pixels of a modified image are output in parallel. By implementing the photo-detector, morphological processing circuitry and LCD output all on a VLSI chip, the array processor is capable is achieving real-time processing of two-dimensional im…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.