Microcomputer having 16 bit fixed length instruction format
US5682545A · kind A · utility
54Cited by
11References
33Claims
0Family size
Assignees
Inventors
- Shumpei Kawasaki
- Eiji Sakakibara
- Kaoru Fukada
- Takanaga Yamazaki
- Yasushi Akao
- Shiro Baba
- Toshimasa Kihara
- Keiichi Kurakazu
- Takashi Tsukamoto
- Shigeki Masumura
- Yasuhiro Tawara
- Yugo Kashiwagi
- Shuya Fujita
- Katsuhiko Ishida
- Noriko Sawa
- Yoichi Asano
- Hideaki Chaki
- Tadahiko Sugawara
- Masahiro Kainaga
- Kouki Noguchi
- Mitsuru Watabe
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.