Manufacturing method for ROM array with minimal band-to-band tunneling

US5683925A · kind A · utility

Assignees

• Waferscale Integration, Inc. · US
• American Microsystems, Inc. · US

Inventors

• Rustom Irani · Santa Clara, US
• Reza Kazerounian · Fremont, US
• Mark Michael Nelson · Pocatello, US

Key dates

• Filing date: Jun 13, 1996
• Grant date: Nov 4, 1997
• Expiry date: Jun 13, 2016

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.