Self-configuring bus
US5684411A · kind A · utility
9Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Oct 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Integrated circuit design contemplating alternate applications incorporates devices, e.g. a gatable pull-down FET resistor, responsive to signal activity at an integrated circuit pin. Signal activity, as opposed to traditional configuration mechanisms, dictates integrated circuit functions including level-pulling functions and bus configuration functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.