Condensed single block PLA plus PAL architecture
US5684413A · kind A · utility
4Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1996 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Mar 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A condensed single block plus PLA architecture utilizing a rectangular shape is shown. By interleaving the ORterms of the PLA array with the Pterms of the array, a significant amount of die space is saved when incorporating the circuit with silicon. The decode routing required is now simplified and the propagation delay skews through the array are also reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.