Erasable and programmable single chip clock generator
US5684434A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Oct 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.