A/D converter with charge-redistribution DAC and split summation of main and correcting DAC outputs
US5684487A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital (A/D) converter of the successive-approximation type wherein the digital-to-analog converter (DAC) includes a charge-redistribution, binary-weighted switched-capacitor array for producing the analog output for comparison with the analog input signal. A second switched-capacitor DAC is employed to develop error correction signals to be combined with the analog signal from the A/D conversion DAC. The conversion DAC array is connected to one input terminal of the comparator, and the error-correction DAC array is connected to the other comparator input terminal, an arrangement which reduces the number of capacitors required while providing symmetrical capacitance loading of the comparator input circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.