Microprocessor executing multiple register transfer operations with a single instruction with derivation of destination register numbers from source register
US5684983A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Feb 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a register file that outputs data from multiple registers at one time, and that stores separate data to multiple registers at one time, and an instruction decoder for decoding an instruction to output an operation control signal. The instruction decoder decodes a specific data transfer instruction and outputs a multiple transfer control signal indicating data transfer from multiple registers to multiple registers, a source designating signal for designating multiple source registers, and a destination designating signal for designating destination registers. The register file responds to the source designating signal and outputs data from corresponding registers. The microprocessor further includes an ALU responsive to the control signal for carrying out an operation according to data stored in the register file to provide the result to a register in the register file. The ALU responds to the multiple transfer control signal and provides data read out from the source registers specified according to the source designating signal to the register file. The register file stores data provided from the ALU to the destination registers specified according to the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.