Segregation of thread-specific information from shared task information
US5684993A · kind A · utility
58Cited by
8References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1996 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Apr 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system includes memory and at least two central processing units (CPUs) that may execute different threads of computation of a same task at the same time. CPU-specific data is segregated from shared task information of different threads of computation of the task. In particular, the shared task information is placed in memory locations of the memory that are directly addressable by both CPUs, and CPU-specific data are placed in memory locations that are directly addressable by only the associated CPU. No additional hardware is needed, and the memory and run-time costs of the invention are miniscule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.