Method for fabricating semiconductor device
US5686327A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device, capable of forming an element-isolating insulating film for MOS transistors in a self-aligned manner during formation of the MOS transistors on a substrate, thereby simplifying the fabrication of the semiconductor device. The substrate is vertically etched to form a protruded portion thereof. By the vertical height of the protruded substrate portion, the gate length of each corresponding MOS transistor can be adjusted. This results in an improvement in the integration degree of the semiconductor device. Accordingly, it is possible to easily apply the least design method to design of highly integrated semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.