Method and apparatus for aligning data for transfer between a source memory and a destination memory over a multibit bus
US5687328A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 1995 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | May 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data alignment logic cell properly aligns the individual data units (e.g., bytes) in a block of data that is transferred in a multiple bit bus such that the data units in the block are transferred to desired lanes of the bus. The data alignment logic cell includes a gathering unit, which aligns the data units into a fixed, justified arrangement in the bus, and a scattering unit, which receives the data units from the gathering unit and realigns them to the desired lanes. Both the gathering and scattering units contain registers for temporarily storing certain of the data units and multiplexers for transferring the data units between the lanes of the bus, the state of the multiplexers being determined by signals from control units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.