High speed, reduced power memory system implemented according to access frequency
US5687382A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a first memory area (MEM-A) implemented using memory units including low threshold voltage transistors powered by a low supply voltage source, and a second memory area (MEM-B) implemented using memory units including higher threshold voltage cells powered by a higher supply voltage source. The first memory area, MEM-A, is designated to contain frequently accessed variables, with less frequently accessed variables designated for storage in the second memory area, MEM-B. The most frequently accessed variables stored in MEM-A provide for fast access at a low power per access power dissipation level due to the lower supply voltage and lower threshold voltage design. Alternatively, the less frequently accessed variables stored in MEM-B require a high power per access, but negligible leakage current during static steady state conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.