Planarizing process for field emitter displays and other electron source applications
US5688158A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1995 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Aug 24, 2015 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0126
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A planarization method for use during manufacture of a microelectronic field emitter device, comprising applying a glass frit slurry including glass particles in a removable base, and subsequently baking to liquify the frit. The invention relates in another aspect to a method of making a microelectronic field emitter device, comprising the steps of: applying a patterned layer of liftoff profile resist over a substrate to define emitter conductor locations; employing the patterned resist layer to form trenches in the substrate at the emitter conductor locations; depositing emitter conductor metal in the trenches and over the patterned resist layer; removing the patterned resist layer; depositing a current limiter layer over the conductors and substrate areas between trenches; depositing a layer of emitter material; pattern masking and etching the layer of emitter material to form emitter structures; depositing gate dielectric; applying a patterned layer of liftoff profile resist over the gate dielectric; evaporating gate metal; and removing the patterned resist layer to define gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.