Method of fabricating a twin - well CMOS device
US5688710A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/007
Abstract
A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a P-type semiconductor silicon wafer. Then, the alignment mark photoresist pattern is formed by the conventional lithography technique, where the alignment mark region is in clear field, while other regions are in dark field. Next, the nitride layer is patterned by plasma-etching technique to form the nitride alignment mark. The N-well region is formed by lithography and ion-implantation techniques. Thereafter, the P-well region is formed by lithography and ion-implantation methods again. Next, the active device region photoresist is formed by lithography technique. The nitride layer is partially etched to open the windows by plasma-etching technique. The P-well region photoresist is then formed, followed by the deep-implantation process. The second P-well region photoresist is then formed, followed by the deep-implantation process. The field oxide regions for isolation are also grown in the window openings during the P-field drive-in step. Finally, the remaining of nitride layer is removed. T…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.