Switched current differentiator
US5689205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A switched current differentiator includes first and second interconnected current memory cells, An input current is applied to terminal (1) and is fed on line (2) to the current memory cells, A first output current is derived from the first current memory cell via a transistor and a second output current is derived from the second current memory cell via another transistor. The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output via a switch on odd phases of a clock signal and is fed directly to the output via a further switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feeback loop. In a fully differential version of the differentiator the inverters may be constructed by the correct interconnection of the differential signals, i.e. by crossing over connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.