Decoding circuit for runlength codes
US5689254A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1995 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Oct 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
After all the data words stored in a first scan transform RAM are initialized to "0"s, only signed level data words are overwritten, based on zero runlength data words, on "0"s at the positions designated by zigzag scan addresses in the first scan transform RAM. Thus, while only non-zero components out of 8.times.8 components forming one block are written in the first scan transform RAM, a block stored in a second scan transform RAM is read and initialized. Further, while only non-zero components of the next block are written in the second scan transform RAM, the block stored in the first scan transform RAM is read and initialized. This achieves, in real time, highly efficient runlength decoding responsive to a picture element clock signal of high frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.