Semiconductor memory device
US5689463A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1995 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Oct 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND type EEPROM includes block selecting circuits (BSC1 to BSC6) configured to keep a defective block non-selected in the mode for simultaneous writing and simultaneous erasure of all blocks (BLK1-BLK4) to test the device, after the defective block is replaced by a redundant block (SBLK1, SBLK2). This prohibitor a high voltage boosted by a booster circuit for simultaneous writing and simultaneous erasure of all blocks from being applied to the defective block. The block selecting circuits output a "NON-SELECT" signal when a signal instructing simultaneous writing or simultaneous erasure of all blocks is supplied after corresponding fuses (fa-fh)are blown or cut off. Therefore, once a defective block is replaced by a redundant block, there never occurs a voltage drop which may otherwise be caused by leakage of current from the defective block, and the device can be used as a non-defective NAND type EEPROM in all modes including the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.