Parallel processing of digital signals in a single arithmetic/logic unit
US5689592A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1993 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Dec 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of processing a digital signal wherein multiple signal values are simultaneously operated upon in a single register. The register is not segmented in hardware, but is segmented by operation of a controlling computer software program. The controlling computer software arranges the digital signal in a computer memory in such a manner as to permit the register to be loaded with a plurality of digital samples, each having a precision less than the total precision available in the register. The method may include steps to partially compensate for errors introduced by carries from one segment of the register to another segment of the register, when necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.