Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
US5689680A · kind A · utility
9Cited by
17References
3Claims
0Family size
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Key dates
| Filing date | Jul 15, 1993 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Jul 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A "bit-sliced" construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be "overlapped", and even operate simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.