Apparatus and method for analyzing circuits using reduced-order modeling of large linear subscircuits
US5689685A · kind A · utility
24Cited by
26References
22Claims
0Family size
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Key dates
| Filing date | Jun 9, 1995 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Jun 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit analyzer and method are disclosed for generating and outputting a Matrix Pade via Lanczos (MPVL) approximation of a frequency response of a circuit from input circuit parameters. A processing unit has a memory for storing circuit characteristic data representing a circuit; a program for generating matrix transfer function data relating to a matrix transfer function associated with the circuit characteristic data; a processor for executing the program; and the processing unit generates the frequency response signal in response to the matrix transfer function data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.