Computer bus utilization determination apparatus
US5689691A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1995 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Nov 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry for monitoring the idle periods on the EISA bus and a program using this known value to determine percentage utilization of the EISA bus. A counter is used to count the number of synchronizing clock periods during which the EISA bus is idle. To determine if the EISA bus is idle, certain logic monitors the EISA bus signals and the arbiter activity to determine if cycles are actually occurring. If so, the EISA bus is not idle and the counter is not incremented. If there is no activity, the counter increments on each BCLK clock. The computer system periodically reads this counter. The computer system determines the interval between read operations of the counter and uses this interval in combination with the counter value and BCLK signal rate to determine the percentage utilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.