Voltage level translator circuit
US5691654A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0175
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of limiting or translating the voltages of input signals, and of generating output signals such that the input's high state and low state differ by a different voltage than the output's high and low state. The present invention also teaches a system comprising a level translator circuit having level translators controlled by an operational amplifier or by a Zener diode that regulates the voltage level on one side of the translators, the other side of the translators being regulated by an external power supply. The operational amplifier or Zener diode, in some embodiments of the present invention, ensures that the second side of the level translators are limited to a given reference voltage. Often, a resistor is connected to the Zener diode or to the output of the operational amplifier, and in some embodiments a resistor-capacitor network removes higher-frequency components from the voltage supply. The invention includes a system level embodiment, in which the voltage level translators protect a memory and bus from voltage levels that would otherwise cause damage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.