Data link module for time division multiplexing control systems
US5691659A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Nov 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/4026
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection circuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programing circuit (232) for accepting programing over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.