Clock synchronization scheme for fractional multiplication systems
US5691660A · kind A · utility
15Cited by
26References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Nov 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.