System and method for increasing throughput of inter-network gateways using a hardware assist engine
US5691985A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Apr 19, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/902
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high bandwidth gateway comprises a source of packet traffic wherein received packets are stored in a buffer, a destination interface circuit for the packets, a microprocessor and a bus that interconnects the components. The microprocessor, which in the prior art controls data transfers, periodically gives up control to a hardware assist engine. The hardware assist engine detects the presence of packets in the source buffer and causes the source buffer to output one or more packets to the destination directly, thus by-passing the microprocessor completely. By this system, bandwidth is improved by the source and the destination working together directly, without having the overhead associated with microprocessor-based or initiated data transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.