Data transmission protection circuit with error correction
US5691998A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | May 10, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A protect circuit that may be interconnected to two different data transmission lines and that provides enhanced error correction. The circuit includes first and second line build-out circuits and fixed delay buffers interconnected to the two transmission lines, as well as a controller and switch. The build-out circuits allow the data bits received from the two data transmission lines to be correlated. Each of the fixed delay buffers has a predetermined length and holds a sequence from one of the two transmission lines. The controller tests the correlated data bits from the build-out circuits to determine whether any coding rule violation has occurred. If a coding error, such as, for example, a hi-polar violation, is detected, the contents of the fixed delay buffer that includes the bit that does follow the predetermined coding rule is transmitted to the receiving station. Thus, both of the transmission lines are utilized in order to enhance the accuracy of the data transmitted to the receiving station.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.