Apparatus for reducing capacitive loading of clock and shift signals by shifting register-based devices
US5692026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1996 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | May 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A shift register, circular pointer or ring counter presents a reduced capacitive load on the clock and shift signals used to control it. The device is constructed using one or more enhanced data cells. Each data cell has a data input, a data output, a clock input and a shift input. The data output of each cell is coupled to the data input of an adjacent cell. At least one pass-AND gate is provided for each cell. The pass-AND gate has a switching input and a switched input. The switching input operates to toggle the input capacitance of the switched input between a larger and a smaller value. The logical OR of the data input and data output of each cell is used to drive the switching input of the associated pass-AND gates for that cell. The switched input of the pass-AND gate is adapted to be coupled to the clock (or shift) signal, and the output of the pass-AND gate is coupled to the clock (or shift) input of the data cell. When two such pass-AND gates are provided for each cell, one may be used for the clock signal, and the other for the shift signal. In this manner, only those cells of the shift register, circular pointer or ring counter whose outputs are asserted, or will become…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.