Block replacement method in cache only memory architecture multiprocessor
US5692149A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Mar 16, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Mar 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block replacement method for use in a bus-based cache only memory architecture multiprocessor, is invoked when a block in a local memory of a first processing node in the multiprocessor is to be replaced to make a space for an incoming block supplied via a system bus from a local memory of a second processing node in the multiprocessor, and includes the following steps: (a) if the block of the first processing node is in an invalid state, or in a shared state, overwriting the block of the first processing node with the incoming block from the second processing node; (b) if the block of the first processing node is in an exclusive state, or in a shared owner state, relocating the block of the first processing node to a third processing node in the multiprocessor, selected in accordance with a predetermined priority scheme, and then overwriting the block of the first processing node with the incoming block from the second processing node; and (c) if the third single processing node cannot be determined among the processing nodes in the multiprocessor with the predetermined priority scheme in step (b), swapping the block of the first processing node for the incoming block from the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.