Bridge circuit for preventing data incoherency by holding off propagation of data transfer completion interrupts until data clears the bridge circuit
US5692200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Oct 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bridge circuit for holding off primary interrupts signaling the completion of a block data transfer from a second bus to a system bus until the data has cleared the bridge circuit. The bridge circuit includes an interrupt control circuit for receiving up to seven primary interrupt signals corresponding to seven sets of bus grant-request lines on a second bus. Each bus grant-request set is assigned a data FIFO for synchronizing the transfer of data from the second bus to a system bus. The interrupt control circuit provides an interrupt to the system bus which corresponds to the primary interrupt only after the associated data FIFO is empty, thereby preventing data coherency problems in system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.