Digital signal processing system with dual memory structures for performing simplex operations in parallel
US5692207A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1994 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processing system includes a first and second memory coupled to first and second register banks respectively. The system further includes first and second multipliers coupled to the first and second register banks for producing first and second product outputs respectively. The system also includes an arithmetic logic unit having first, second and third inputs and an output. The first input is coupled to the first product output and the second and third inputs are selectively coupled to either of the second product output and the first and second register means. The arithmetic logic unit output is coupled to the first and second register banks for accumulating the sample values in the first and second register banks. The system further includes Instruction control for storing a plurality of instruction op codes and controlling the system to compute the sample values by performing simplex operations during each cycle of a plurality of operating cycles of a digital signal processing procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.