Method for fabricating BiCMOS device
US5693555A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Jun 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method for fabricating a bipolar complementary metal oxide semiconductor device, includes a first step of forming a three-layered substrate of p.sup.- /n.sup.+ /n.sup.- type or n.sup.- /p.sup.+ /p.sup.- type and forming p- and n-wells to be adjacent to each other to the bottom of the top layer of the three-layered substrate; a second step of isolating the p- and n-wells from each other and defining a region for a bipolar transistor on one side to separate base/emitter regions from each other; a third step of defining a gate region to form a metal- oxide semiconductor transistor in each of the p- and n-wells and forming collector/emitter regions in the bipolar transistor region; and a fourth step of forming an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor and a bipolar transistor on the p-well, n-well and collector/emitter regions, respectively, and forming source/drain and base electrodes through diffusion by using a doped polycrystalline silicon sidewall spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.