Process for the laminar joining of silicon semiconductor slices

US5693574A · kind A · utility

Assignee

• Deutsche Aerospace AG · DE

Inventors

• Gunther Schuster · Bad Boll, DE
• Klaus Panitsch · Tauberbischofsheim, DE

Key dates

• Filing date: Feb 4, 1994
• Grant date: Dec 2, 1997
• Expiry date: Feb 4, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/058
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for the laminar joining of two or more silicon semiconductor slices (wafers) under the effect of pressure and heat, in which a thin layer of a semiconductor-compatible material is applied to at least one of the surfaces to be joined.