Zero static power programmable logic cell
US5694055A · kind A · utility
2Cited by
4References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Feb 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A zero static power programmable logic cell that operates without I.sub.cc leakage in the circuit being driven when the control nodes are set to V.sub.cc or ground, and has a decreased switching skew is provided. The logic cell utilizes stacked transistors and separates the output node from the input nodes by forming an inverter stage based on the current state of operation. The inverter stage isolates the output node from the input nodes, while also providing gain to the next stage. This configuration provides for a more compact cell design and prevents I.sub.cc leakage in the circuitry being driven by the logic cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.